Memory devices and systems are common in computers and other electronic devices. There are many different types of memory including flash memory. Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Two common types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic memory cell configuration or each is arranged. A NAND array can have memory cells that employ a single field effect transistor (FET). The cells can be arranged in an array where the transistors/cells have floating gates in a matrix such that the gates of each floating gate memory cell of the array are coupled by rows to word select lines. Each memory cell in the array is coupled together in series or in a string configuration, source to drain, between a source line and a column bit line.
A typical floating gate memory cell is fabricated in an integrated circuit substrate and includes a source region and a drain region that is spaced apart from the source region to form an intermediate channel region. A conductive floating gate, typically made of doped polysilicon, or non-conductive charge trapping layer (a floating node), such as nitride (as would be utilized in a silicon-oxide-nitride-oxide-silicon or SONOS gate-insulator stack), is disposed over the channel region and is electrically isolated from the other cell elements by a dielectric material, typically an oxide.
A tunnel oxide can be formed between the floating gate/node and the channel region. A control gate can be located over the floating gate/node and is typically made of doped polysilicon or metal. The control gate can be electrically separated from the floating gate/node by another dielectric layer. Thus, the floating gate or charge trapping layer/floating node is “floating” in dielectric so that it is insulated from both the channel and the control gate. Charge is transported to, or removed from the floating gate or trapping layer by specialized programming and erase operations, respectively, altering the threshold voltage of the device. In accordance with the embodiments provided herein, improved methods for programming and altering the threshold voltage of memory cells/transistors is disclosed
As stated above, an array of cells/transistors can be coupled together in series, source to drain, between a source line and a column bit line. In practice, a string typically has 8, 16, 32, or more cells. Each floating gate/node memory cell FET has a gate-insulator stack formed over the channel region. In one embodiment, each string can be formed in an isolation trench, allowing the substrate of each isolation trench to be individually biased for programming and erasure. In each NAND memory string, impurity (N+ typically) doped regions can be formed between each gate insulator stack to form the source and drain regions of the adjacent memory cells, which additionally can operate as connectors to couple the cells of the NAND string together. In one embodiment, the N+doped regions can be omitted and a single channel region is formed under the NAND memory string, coupling the individual memory cells. The disclosed NAND memory can be implemented with silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor structure, as well as other semiconductor structures known in the art.
Each transistor can be viewed as a single memory cell and a memory array can have millions of cells. Such a memory cell configuration can be accessed by a row decoder activating a row of memory cells by selecting the word select line (WL) coupled to transistor gates. In addition, the word lines coupled to the gates of the unselected memory cells of each string can also be driven during reading writing/programming and erasing procedures. However, the unselected memory cells of each string are typically driven at a higher gate voltage so as to operate them as pass transistors allowing unselected cells to pass current in a manner that is unrestricted by their stored data values.